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vishay siliconix si3456ddv new product document number: 69075 s09-1399-rev. b, 20-jul-09 www.vishay.com 1 n-channel 30-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfet ? compliant to rohs directive 2002/95/ec applications ? load switch ? hdd ? dc/dc converter product summary v ds (v) r ds(on) ( ) i d (a) d q g (typ.) 30 0.040 at v gs = 10 v 6.3 2.8 nc 0.050 at v gs = 4.5 v 5.7 marking code ay xxx lot tracea b ility and date code part # code orderin g information: si3456dd v -t1-e3 (lead (p b )-free) si3456dd v -t1-ge3 (lead (p b )-free and halogen-free) n -channel mosfet g d s tsop-6 top view 6 4 1 2 3 5 3 mm 2. 8 5 mm d d d d s g (1, 2, 5, 6) (3) (4) notes: a. surface mounted on 1" x 1" fr4 board. b. t = 5 s. c. maximum under steady state conditions is 120 c/w. d. based on t c = 25 c. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 6.3 a t c = 70 c 5.1 t a = 25 c 5.0 a, b t a = 70 c 4.0 a, b pulsed drain current i dm 20 continuous source-drain diode current t c = 25 c i s 2.2 t a = 25 c 1.4 a, b maximum power dissipation t c = 25 c p d 2.7 w t c = 70 c 1.7 t a = 25 c 1.7 a, b t a = 70 c 1.1 a, b operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, c t 5 s r thja 61 74 c/w maximum junction-to-foot (drain) steady state r thjf 38 46
www.vishay.com 2 document number: 69075 s09-1399-rev. b, 20-jul-09 vishay siliconix si3456ddv new product notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 30 v v ds temperature coefficient v ds /t j i d = 250 a 32 mv/c v gs(th) temperature coefficient v gs(th) /t j - 5 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.2 3 v gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v 1 a v ds = 30 v, v gs = 0 v, t j = 70 c 10 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 15 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 5.0 a 0.033 0.040 v gs = 4.5 v, i d = 4.5 a 0.041 0.050 forward transconductance a g fs v ds = 15 v, i d = 5.0 a 15 s dynamic b input capacitance c iss v ds = 15 v, v gs = 0 v, f = 1 mhz 325 pf output capacitance c oss 60 reverse transfer capacitance c rss 30 total gate charge q g v ds = 15 v, v gs = 10 v, i d = 5 a 69 nc v ds = 15 v, v gs = 4.5 v, i d = 5 a 2.8 4.2 gate-source charge q gs 1.1 gate-drain charge q gd 0.8 gate resistance r g f = 1 mhz 0.6 2.8 5.6 tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 3.8 i d ? 4 a, v gen = 4.5 v, r g = 1 12 18 ns rise time t r 13 20 turn-off delay time t d(off) 16 25 fall time t f 11 17 tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 3.8 i d ? 4 a, v gen = 10 v, r g = 1 48 rise time t r 918 turn-off delay time t d(off) 11 20 fall time t f 815 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 1.2 a pulse diode forward current i sm 20 body diode voltage v sd i s = 4 a, v gs = 0 v 0.8 1.2 v body diode reverse recovery time t rr i f = 4 a, di/dt = 100 a/s, t j = 25 c 11 20 ns body diode reverse recovery charge q rr 48nc reverse recovery fall time t a 6 ns reverse recovery rise time t b 5
document number: 69075 s09-1399-rev. b, 20-jul-09 www.vishay.com 3 vishay siliconix si3456ddv new product typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current gate charge 0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 2.5 v gs = 10 v thr u 4 v v gs =3 v v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 0.02 0.03 0.04 0.05 0.06 0 5 10 15 20 v gs = 4.5 v v gs =10 v - on-resistance ( ) r ds(on) i d - drain c u rrent (a) 0 2 4 6 8 10 0123456 i d = 5.0 a v ds =24 v v ds =15 v - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs transfer characteristics capacitance on-resistance vs. junction temperature 0 1 2 3 4 5 01234 t c = 25 c t c = 125 c t c =- 55 c v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d c rss 0 100 200 300 400 0 5 10 15 20 25 30 c iss c oss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) 0.7 0.9 1.1 1.3 1.5 1.7 - 50 - 25 0 25 50 75 100 125 150 v gs =4.5 v ;i d =4.5 a v gs =10 v ;i d =5.0 a t j -j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on)
www.vishay.com 4 document number: 69075 s09-1399-rev. b, 20-jul-09 vishay siliconix si3456ddv new product typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.1 1 10 100 0.0 0.3 0.6 0.9 1.2 1.5 t j = 150 c t j = 25 c v sd -so u rce-to-drain v oltage ( v ) - so u rce c u rrent (a) i s 1.1 1.3 1.5 1.7 1.9 2.1 2.3 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a ( v ) v gs(th) t j - temperat u re (c) on-resistance vs. gate-to-source voltage single pulse power 0.00 0.02 0.04 0.06 0.0 8 0.10 0246 8 10 t j =25 c t j =125 c - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) power (w) time (s) 0 5 10 15 20 25 0.001 0.01 0.1 1 10 100 safe operating area, junction-to-ambient 100 1 0.1 1 10 100 0.01 10 0.1 v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified - drain c u rrent (a) i d t a =25 c single p u lse 100 a limited b yr ds(on) * b v dss limited 1ms 10 ms 100 ms 1s,10s dc
document number: 69075 s09-1399-rev. b, 20-jul-09 www.vishay.com 5 vishay siliconix si3456ddv new product typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* t c - case temperat u re (c) i d - drain c u rrent (a) 0 2 4 6 8 0 25 50 75 100 125 150 power derating (t c ) t c - case temperat u re (c) po w er ( w ) 0.0 0.7 1.4 2.1 2. 8 3.5 0 25 50 75 100 125 150 power derating (t a ) t a -am b ient temperat u re (c) po w er ( w ) 0.0 0.3 0.6 0.9 1.2 1.5 0 25 50 75 100 125 150
www.vishay.com 6 document number: 69075 s09-1399-rev. b, 20-jul-09 vishay siliconix si3456ddv new product typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69075 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 square wave pulse duration (s) normalized effective transient thermal impedance 1 0.1 0.01 t 1 t 2 notes: p dm 1. duty cycle, d = 2. per unit base = r thja = 120 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. surface mounted duty cycle = 0.5 single pulse 0.02 0.05 normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 0 1 1 10 -1 10 -4 0.2 0.1 duty cycle = 0.5 square wave pulse duration (s) normalized effective transient thermal impedance 1 0.1 0.01 0.05 0.02 single pulse
vishay siliconix package information document number: 71200 18-dec-06 www.vishay.com 1 1 2 3 g au ge pl a ne l 5 4 r r c 0.15 m b a b c 0.0 8 0.17 ref s e a ting pl a ne -c- s e a ting pl a ne a 1 a 2 a -a- d -b- e 1 e l 2 (l 1 ) c 4x 1 4x 1 e e1 1 2 3 6 5 4 c 0.15 m b a b -b- e 1 e e e1 5-lead tsop 6-lead tsop tsop: 5/6?lead jedec part number: mo-193c millimeters inches dim min nom max min nom max a 0.91 - 1.10 0.036 - 0.043 a 1 0.01 - 0.10 0.0004 - 0.004 a 2 0.90 - 1.00 0.035 0.03 8 0.039 b 0.30 0.32 0.45 0.012 0.013 0.01 8 c 0.10 0.15 0.20 0.004 0.006 0.00 8 d 2.95 3.05 3.10 0.116 0.120 0.122 e 2.70 2. 8 5 2.9 8 0.106 0.112 0.117 e 1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.95 b s c 0.0374 b s c e 1 1. 8 0 1.90 2.00 0.071 0.075 0.079 l 0.32 - 0.50 0.012 - 0.020 l 1 0.60 ref 0.024 ref l 2 0.25 b s c 0.010 b s c r 0.10 - - 0.004 - - 0 4 8 0 4 8 1 7 nom 7 nom ecn: c-06593-rev. i, 1 8 -dec-06 dwg: 5540
an823 vishay siliconix document number: 71743 27-feb-04 www.vishay.com 1 mounting little foot tsop-6 power mosfets surface mounted power mosfet packaging has been based on integrated circuit and small signal packages. those packages have been modified to provide the improvements in heat transfer required by power mosfets. le adframe materials and design, molding compounds, and die attach materials have been changed. what has remained the same is the footprint of the packages. the basis of the pad design for surface mounted power mosfet is the basic footprint for the package. for the tsop-6 package outline drawing see http://www.vishay.com/doc?71200 and see http://www.vishay.com/doc?72610 for the minimum pad footprint. in converting the footprint to th e pad set for a power mosfet, you must remember that not only do you want to make electrical connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package. in the case of the tsop-6 package, the electrical connections are very simple. pins 1, 2, 5, and 6 are the drain of the mosfet and are connected together. for a small signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. also, heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources when looking at heat spread on the pc board. figure 1 shows the copper spreading recommended footprint for the tsop-6 package. this pattern shows the starting point for utilizing the board area available for the heat spreading copper. to create this pattern, a plane of copp er overlays the basic pattern on pins 1,2,5, and 6. the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and star t the process of spreading the heat so it can be dissipated into th e ambient air. notice that the planar copper is shaped like a ?t? to move heat away from the drain leads in all directions. this pattern uses all the available area underneath the body for this purpose. figure 1. recommended copper spreading footprint 0.049 1.25 0.010 0.25 0.014 0.35 0.074 1.875 0.122 3.1 0.026 0.65 0.167 4.25 0.049 1.25 since surface mounted packages are small, and reflow soldering is the most common form of soldering for surface mount components, ?thermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum power trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. reflow soldering vishay siliconix surface-mount packages meet solder reflow reliability requirements. devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, hast, or pressure pot. the solder reflow temperature profile used, and the temperatures and time duration, are shown in figures 2 and 3. ramp-up rate +6 c/second maximum temperature @ 155 15 c 120 seconds maximum temperature above 180 c 70 ? 180 seconds maximum t emperature 240 +5/ ? 0 c time at maximum t emperature 20 ? 40 seconds ramp-down rate +6 c/second maximum figure 2. solder reflow temperature profile
an823 vishay siliconix www.vishay.com 2 document number: 71743 27-feb-04 255 ? 260 c 1 4 c/s (max) 3-6 c/s (max) 10 s (max) reflow zone pre-heating zone 3 c/s (max) 140 ? 170 c maximum peak temperature at 240 c is allowed. figure 3. solder reflow temperature and time durations 60-120 s (min) 217 c 60 s (max) thermal performance a basic measure of a device?s thermal performance is the junction-to-case thermal resistance, r jc , or the junction-to-foot thermal resistance, r jf . this parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. table 1 shows the thermal performance of the tsop-6. table 1. equivalent steady state performance?tsop-6 thermal resistance r jf 30 c/w system and electrical impact of tsop-6 in any design, one must take into account the change in mosfet r ds(on) with temperature (figure 4). 0.6 0.8 1.0 1.2 1.4 1.6 ? 50 ? 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 6.1 a on-resistance vs. junction temperature t j ? junction temperature ( c) figure 4. si3434dv r ds(on) ? on-resiistance (normalized)
application note 826 vishay siliconix www.vishay.com document number: 72610 26 revision: 21-jan-08 application note recommended minimum pads for tsop-6 0.119 (3.023) recommended mi nimum pads dimensions in inches/(mm) 0.099 (2.510) 0.064 (1.626) 0.028 (0.699) 0.039 (1.001) 0.020 (0.508) 0.019 (0.493) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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